10.1 Notes on CACHE Instruction Operations

Address Error Exception

During an Index CacheOp, bit 0 is not checked for an Address Error exception since this bit is used as the Way indicator bit, and may be non-zero. Bit 1 of an Index CacheOp can still generate an Address Error exception if it is not set to zero.

For all remaining CacheOps, the low-order two bits of the instruction must be set to zero, or else they will generate an Address Error exception.

A CacheOp is never checked for alignment Address Error exceptions, only for privilege-type Address Error exceptions.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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